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Chisel Community Conference

Milpitas, CA | January 29-30, 2020
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9:00am AKST

Intro to CHIPS Alliance - Zvonimir Bandic, Western Digital Corporation Auditorium

9:15am AKST

Latest Updates on Chisel - Adam Izraelevitz, SiFive Auditorium

9:40am AKST

Experiences in Using Chisel to Build an Out-of-order Industry Core - Christopher Celio Auditorium

10:00am AKST

A Chisel Implementation of NVDLA - Yuda Wang Auditorium

10:50am AKST

A Chisel-based Programmable Hardware Monitor - Leila Delshadtehrani, Boston University Auditorium

11:10am AKST

The RISC-V Rosetta Stone: Understanding the Diplomacy Parameter Negotiation Framework - Edward Wang, UC Berkeley / MIT Auditorium

11:30am AKST

Tester for Multi-port Modules with Bus Functional Models - Jan Marjanovic, Deutsches Elektronen-Synchrotron DESY Auditorium

1:00pm AKST

Golden Gate: An Optimizing FIRRTL Compiler for FPGA-Accelerated RTL Simulation - David Biancolin Auditorium

1:20pm AKST

A Chisel Backend for Timing Predictability - Mihail Asavoae Auditorium

1:40pm AKST

Framework for Designing Programmable Modules - Allen Baker, ANSYS Auditorium

2:00pm AKST

Is Chisel Ready for Class? - Martin Schoeberl, Technical University of Denmark Auditorium

3:00pm AKST

Improving Chisel/FIRRTL Verilog Generation - Schuyler Eldridge, IBM T.J. Watson Research Center Auditorium

3:20pm AKST

A Software Engineer Builds an OpenPOWER Core in Chisel. What Could go Wrong? - Anton Blanchard, IBM Auditorium

3:30pm AKST

Chsielminer: A Parametrizable Generator Blockchain Mining - Edward Wang, UC Berkeley / MIT Auditorium

4:00pm AKST

Event Wrap Up and Summary MP Room 1