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Chisel Community Conference

Milpitas, CA | January 29-30, 2020
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8:00am AKST

Morning Coffee

Wednesday January 29, 2020 8:00am - 9:00am AKST
Auditorium

8:00am AKST

Registration

Wednesday January 29, 2020 8:00am - 4:00pm AKST
Building #1, Main Lobby - Front Desk

Registration + Badge Pick-up

9:00am AKST

Intro to CHIPS Alliance - Zvonimir Bandic, Western Digital Corporation

Speakers

Zvonimir Bandic

Senior Director, Western Digital

Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and... Read More →

Wednesday January 29, 2020 9:00am - 9:15am AKST
Auditorium

9:15am AKST

Latest Updates on Chisel - Adam Izraelevitz, SiFive

Speakers

Adam Izraelevitz

Staff Engineer, SiFive

Adam Izraelevitz is a staff engineer at SiFive working on Chisel and FIRRTL development. He recently received his PhD in Electrical Engineering and Computer Science at UC Berkeley in 2019. His interests include hardware design methodology, programming languages, compilers and computer... Read More →

Wednesday January 29, 2020 9:15am - 9:40am AKST
Auditorium

9:40am AKST

Experiences in Using Chisel to Build an Out-of-order Industry Core - Christopher Celio

This talk will cover some of the experiences of a start-up using rocket-chip and riscv-boom to build an out-of-order core. Most of the effort went into adding reliability, test, and debug features and into interfacing with the rest of the company's standard flow. Some of the challenges included instantiating and interfacing with foundry SRAMs, properly constraining clock domain crossings, and managing X-propagation issues. But generally speaking, we found Chisel very productive for designers._x000D_

Speakers

Christopher Celio

CPU Architect

Chris Celio graduated with a PhD from UC Berkeley where he was advised by Krste Asanovic and David Patterson. He received his B.S. and M.Eng. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology. For his PhD thesis, he designed and... Read More →

Wednesday January 29, 2020 9:40am - 10:00am AKST
Auditorium

10:00am AKST

A Chisel Implementation of NVDLA - Yuda Wang

soDLA is a self-driving car optimized DLA(or, a so-so DLA), focus on using an agile and standard method to design a large-scale accelerator. soDLA adopts the Chisel implementation of NVDLA(nvgen), and gradually add more next-generation acceleration functions, such as self-driving car package(cora).

Speakers

Yuda Wang

My name is Yuda Wang, currently running a warehouse in downtown Berkeley. I graduated from Master of Advanced Study of Integrated Circuit from Berkeley, and Master of Science in Computers and Microelectronics from Illinois Tech. My Undergrad degree is Bachelor of Science in Microelectronics... Read More →

Wednesday January 29, 2020 10:00am - 10:20am AKST
Auditorium

10:20am AKST

Coffee Break

Wednesday January 29, 2020 10:20am - 10:50am AKST
Auditorium

10:50am AKST

A Chisel-based Programmable Hardware Monitor - Leila Delshadtehrani, Boston University

Leveraging the ease of hardware description in Chisel, we develop a programmable hardware monitor connected to the Rocket core through the RoCC interface. Our monitor can enforce different runtime management and security policies, and assist with profiling and debugging. We prototype our design on an FPGA with the full software stack (including the OS support and user-level APIs) and evaluate the full design for different use cases. Our complete end-to-end design is publicly available.

Speakers

Leila Delshadtehrani

PhD Student, Boston University

Leila Delshadtehrani is a PhD student at Boston University, where she is a member of Integrated Circuits and Systems Group (ICSG). She is interested in hardware security and solutions that provide a full software stack around hardware designs.

Wednesday January 29, 2020 10:50am - 11:10am AKST
Auditorium

11:10am AKST

The RISC-V Rosetta Stone: Understanding the Diplomacy Parameter Negotiation Framework - Edward Wang, UC Berkeley / MIT

Researchers interested in building RISC-V SoCs with rocket-chip / diplomacy often find it hard to use due to a lack of documentation on the API and workings of diplomacy. We studied the open source rocket-chip generator so that we could understand and verify the assumptions involved in diplomacy and then present the information in a principled and usable manner for researchers. We discuss the process of understanding diplomacy, our main findings, and potential future work in SoC generator

Speakers

Edward Wang

Graduate Student Researcher, UC Berkeley / MIT

Edward Wang is currently pursuing a PhD in computer science. He is broadly interested in compilers, hardware design, and formal verification, and is a contributor to the Chisel and FIRRTL projects. He obtained his B.S. and M.S. degrees from UC Berkeley. You can contact him at edw... Read More →

Wednesday January 29, 2020 11:10am - 11:30am AKST
Auditorium

11:30am AKST

Tester for Multi-port Modules with Bus Functional Models - Jan Marjanovic, Deutsches Elektronen-Synchrotron DESY

Presented here is a new tester for Chisel, providing parallel execution of Bus Functional Models in a testbench. This greatly simplifies testing of the designs with several ports, and it also provides more flexibility than OrderedDecoupledHWIOTester from Chisel Testers.

The tester inherits from PeekPokeTester and uses Scala Reflection to find all instances which need to be updated every clock cycle. Two examples are also shown to illustrate the advantages of the new approach.

Speakers

Jan Marjanovic

Firmware Developer, Deutsches Elektronen-Synchrotron DESY

Jan Marjanovic has received a Diploma in Electrical Engineering in 2014 from University of Ljubljana, Slovenia. Currently he works as a firmware developer at DESY in Hamburg, Germany where he focuses on development of various electronic components for particle accelerator instrumentation... Read More →

ccc2020 marjanovic bfm tester rev2 pdf

Wednesday January 29, 2020 11:30am - 11:50am AKST
Auditorium

11:50am AKST

Lunch

Wednesday January 29, 2020 11:50am - 1:00pm AKST
Auditorium

1:00pm AKST

Golden Gate: An Optimizing FIRRTL Compiler for FPGA-Accelerated RTL Simulation - David Biancolin

Golden Gate (MIDAS II) is the latest generation of FIRRTL compiler design at UCB-BAR for doing cycle-exact FPGA-accelerated RTL simulation, and ships as part of FireSim 1.7.0+. Golden Gate builds on FireSim’s previous compiler, MIDAS, to enable the following

Speakers

David Biancolin

Wednesday January 29, 2020 1:00pm - 1:20pm AKST
Auditorium

1:20pm AKST

A Chisel Backend for Timing Predictability - Mihail Asavoae

From a general point of view, we aim to (re-)expose a specific challenge in safety-critical systems (i.e. the need for strong timing requirements) and a potential solution (i.e. timing guarantees via formal modeling and verification) on Chisel designs. Such systems are needed in avionics or automotive domains. From a more technical point of view, we present an in-depth investigation of the Chisel language semantics and its transformation capabilities (which can be of general interest as well).

Speakers

Mihail Asavoae

Wednesday January 29, 2020 1:20pm - 1:40pm AKST
Auditorium

1:40pm AKST

Framework for Designing Programmable Modules - Allen Baker, ANSYS

Despite Chisel's conveniences for describing hardware, it's still difficult for beginners to create complex logic using basic constructs. I propose a flexible framework for designing modules that process instructions coming from a bus. The structure would be like a textual specification, with state and instructions specified at the top level. Each instruction declares its dependencies and how it will use those to compute results to be stored or sent to other modules.

Speakers

Allen Baker

Lead Software Developer, ANSYS

Allen Baker is a lead software developer at the Semiconductor Business Unit in ANSYS, Inc. He develops tools to help IC engineers predict and reduce power consumption early in the design process. Allen has a M.S. in Electrical Engineering and B.S. in Computer Engineering from the... Read More →

Wednesday January 29, 2020 1:40pm - 2:00pm AKST
Auditorium

2:00pm AKST

Is Chisel Ready for Class? - Martin Schoeberl, Technical University of Denmark

Chisel is aiming for two different types of engineers: hardware designers, knowing Verilog or VHDL and software engineers, knowing object-oriented/functional programming. However, is Chisel ready for being a first programming language?_x000D_
_x000D_
I will switch my digital electronics course for 2nd semester EE students from VHDL to Chisel. Chisel will be their first programming language. I will present the open-source teaching material for this challenge, including a book on "Digital Design with Chisel".

Speakers

Martin Schoeberl

Assoc. Prof., Technical University of Denmark

Martin Schoeberl received his PhD from the Vienna University of Technology in 2005. From 2005 to 2010 he has been Assistant Professor at the Institute of Computer Engineering. He is now Associate Professor at the Technical University of Denmark. His research interest is on hard real-time... Read More →

Wednesday January 29, 2020 2:00pm - 2:20pm AKST
Auditorium

2:20pm AKST

Coffee Break & Poster Session: Kevin Laeufer, Anthony Bisulco & Edward Wang

Wednesday January 29, 2020 2:20pm - 3:00pm AKST
Auditorium

Poster Session Meal Function

3:00pm AKST

Improving Chisel/FIRRTL Verilog Generation - Schuyler Eldridge, IBM T.J. Watson Research Center

Chisel/FIRRTL Verilog code generation has dual requirements: 1) users building ASICs or working with FPGAs care about quality of results (QoR) and 2) verification engineers, hobbyists, and users learning Chisel by inspecting output Verilog often care about the readability of generated Verilog. Towards improving Verilog readability, while not sacrificing QoR, this talk provides an overview of a number of ideas that are merged or in the development pipeline for improving Verilog code generation.

Speakers

Schuyler Eldridge

Research Staff Member, IBM T. J. Watson Research Center

I'm a Researcher with IBM doing work on improving the hardware design and IP integration process with new languages and methods. I'm a maintainer of the Chisel and FIRRTL projects.

Wednesday January 29, 2020 3:00pm - 3:20pm AKST
Auditorium

3:20pm AKST

A Software Engineer Builds an OpenPOWER Core in Chisel. What Could go Wrong? - Anton Blanchard, IBM

In mid 2019 Anton started on an OpenPOWER core in VHDL which was released to Github in August to coincide with the opening of the POWER ISA. That experience led him to look at other hardware languages including Chisel. This talk will run through the experience of building a new core in Chisel from the perspective of a software engineer. Some of the challenges as well as some of the positives will be outlined. A few comparisons of VHDL and Chisel implementations within the two cores will be shown

Speakers

Anton Blanchard

Distinguished Engineer, IBM

Anton has been involved with Linux and Open Source Software for over 20 years, much of that time with IBM. He leads a worldwide team dedicated to using Open Source technologies to build better products. In mid 2019he got the Open Hardware bug as a result of IBM's opening up of the... Read More →

Wednesday January 29, 2020 3:20pm - 3:40pm AKST
Auditorium

3:30pm AKST

Chsielminer: A Parametrizable Generator Blockchain Mining - Edward Wang, UC Berkeley / MIT

Distributed blockchain technology uses Proof of Work (PoW), mainly reversing a cryptographic hash, to prevent malicious actors from taking control of the network. We introduce Chiselminer, a generator for blockchain mining, written in Chisel3. Chiselminer enables specialization via a parametrizable pipeline, storage, and computation (adder) elements. Chiselminer has been implemented in 2 process nodes so far and has been demonstrated to result in performance and power improvements.

Speakers

Edward Wang

Graduate Student Researcher, UC Berkeley / MIT

Edward Wang is currently pursuing a PhD in computer science. He is broadly interested in compilers, hardware design, and formal verification, and is a contributor to the Chisel and FIRRTL projects. He obtained his B.S. and M.S. degrees from UC Berkeley. You can contact him at edw... Read More →

Wednesday January 29, 2020 3:30pm - 4:00pm AKST
Auditorium

8:00am AKST

Morning Coffee

Thursday January 30, 2020 8:00am - 9:00am AKST
MP Room Foyer

8:00am AKST

Registration

Thursday January 30, 2020 8:00am - 4:00pm AKST
Building #2 Lobby

Registration + Badge Pick-up

9:00am AKST

The Chisel Bootcamp - Presented by Richard Lin

Speakers

Richard Lin

UC Berkeley

Richard Lin is a PhD student at UC Berkeley advised by Elad Alon and Bjoern Hartmann. He is interested in improving design processes, with a human factors focus, and has been involved in the development of Chisel and emphasizing features that promote learnability and clarity.

Thursday January 30, 2020 9:00am - 10:00am AKST
MP Room 5

9:00am AKST

Becoming a Chisel Developer - Presented by Schuyler Eldridge, IBM

Speakers

Schuyler Eldridge

Research Staff Member, IBM T. J. Watson Research Center

I'm a Researcher with IBM doing work on improving the hardware design and IP integration process with new languages and methods. I'm a maintainer of the Chisel and FIRRTL projects.

Thursday January 30, 2020 9:00am - 10:00am AKST
MP Room 1

Development Track

10:00am AKST

Coffee Break

Thursday January 30, 2020 10:00am - 10:15am AKST
MP Middle

10:15am AKST

Advanced and New Chisel Features - Presented by Adam Izraelevitz, SiFive

Speakers

Adam Izraelevitz

Staff Engineer, SiFive

Adam Izraelevitz is a staff engineer at SiFive working on Chisel and FIRRTL development. He recently received his PhD in Electrical Engineering and Computer Science at UC Berkeley in 2019. His interests include hardware design methodology, programming languages, compilers and computer... Read More →

Thursday January 30, 2020 10:15am - 11:00am AKST
MP Room 1

Development Track

10:15am AKST

The Chisel Bootcamp continued - Presented by Richard Lin

Speakers

Richard Lin

UC Berkeley

Richard Lin is a PhD student at UC Berkeley advised by Elad Alon and Bjoern Hartmann. He is interested in improving design processes, with a human factors focus, and has been involved in the development of Chisel and emphasizing features that promote learnability and clarity.

Thursday January 30, 2020 10:15am - 12:00pm AKST
MP Room 5

11:00am AKST

Chipyard and FireSim - Presented by Alon Amid and Sagar Karandikar, UC Berkeley

Speakers

Alon Amid

Graduate Student, University of California, Berkeley

Sagar Karandikar

UC Berkeley

Sagar Karandikar is a PhD student in Computer Science at the University of California, Berkeley, focusing in Computer Architecture and Systems. He works in the Berkeley Architecture Research group and the ADEPT and RISE Labs, advised by Krste Asanovic. His research focuses on hardware/software... Read More →

Thursday January 30, 2020 11:00am - 12:00pm AKST
MP Room 1

Periphery Track

12:00pm AKST

Lunch

Thursday January 30, 2020 12:00pm - 1:00pm AKST
MP Middle

1:00pm AKST

HAMMER: A Resusable Methodology for Physical Design - Presented by Colin Schmidt, UC Berkeley)

Speakers

Colin Schmidt

UC Berkeley

Colin Schmidt is a 7th year PhD student at UC Berkeley advised by Krste Asanovic.His research focuses on data-parallel accelerators including their ISA design, VLSI implementation, and compiler toolchain support.He has been involved with RISC-V since he started at Berkeley and has... Read More →

Thursday January 30, 2020 1:00pm - 2:00pm AKST
MP Room 1

Periphery Track

1:00pm AKST

The Chisel Bootcamp continued - Presented by Richard Lin

Thursday January 30, 2020 1:00pm - 3:00pm AKST
MP Room 5

2:00pm AKST

Writing a FIRRTL Transform - Presented by Albert Magyar, UC Berkeley

Thursday January 30, 2020 2:00pm - 3:00pm AKST
MP Room 1

Development Track

3:00pm AKST

Coffee Break

Thursday January 30, 2020 3:00pm - 3:15pm AKST
MP Middle

3:15pm AKST

The Chisel Bootcamp continued - Presented by Richard Lin

Thursday January 30, 2020 3:15pm - 4:00pm AKST
MP Room 5

3:15pm AKST

Demos - Presented by Chick Markley

Thursday January 30, 2020 3:15pm - 4:00pm AKST
MP Room 1

Periphery Track

4:00pm AKST

Event Wrap Up and Summary

Thursday January 30, 2020 4:00pm - 4:15pm AKST
MP Room 1