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Chisel Community Conference

Milpitas, CA | January 29-30, 2020
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8:00am AKST

Morning Coffee Auditorium Registration Building #1, Main Lobby - Front Desk

9:00am AKST

Intro to CHIPS Alliance - Zvonimir Bandic, Western Digital Corporation Auditorium

9:15am AKST

Latest Updates on Chisel - Adam Izraelevitz, SiFive Auditorium

9:40am AKST

Experiences in Using Chisel to Build an Out-of-order Industry Core - Christopher Celio Auditorium

10:00am AKST

A Chisel Implementation of NVDLA - Yuda Wang Auditorium

10:20am AKST

Coffee Break Auditorium

10:50am AKST

A Chisel-based Programmable Hardware Monitor - Leila Delshadtehrani, Boston University Auditorium

11:10am AKST

The RISC-V Rosetta Stone: Understanding the Diplomacy Parameter Negotiation Framework - Edward Wang, UC Berkeley / MIT Auditorium

11:30am AKST

Tester for Multi-port Modules with Bus Functional Models - Jan Marjanovic, Deutsches Elektronen-Synchrotron DESY Auditorium

11:50am AKST

Lunch Auditorium

1:00pm AKST

Golden Gate: An Optimizing FIRRTL Compiler for FPGA-Accelerated RTL Simulation - David Biancolin Auditorium

1:20pm AKST

A Chisel Backend for Timing Predictability - Mihail Asavoae Auditorium

1:40pm AKST

Framework for Designing Programmable Modules - Allen Baker, ANSYS Auditorium

2:00pm AKST

Is Chisel Ready for Class? - Martin Schoeberl, Technical University of Denmark Auditorium

2:20pm AKST

Coffee Break & Poster Session: Kevin Laeufer, Anthony Bisulco & Edward Wang Auditorium

3:00pm AKST

Improving Chisel/FIRRTL Verilog Generation - Schuyler Eldridge, IBM T.J. Watson Research Center Auditorium

3:20pm AKST

A Software Engineer Builds an OpenPOWER Core in Chisel. What Could go Wrong? - Anton Blanchard, IBM Auditorium

3:30pm AKST

Chsielminer: A Parametrizable Generator Blockchain Mining - Edward Wang, UC Berkeley / MIT Auditorium

8:00am AKST

Morning Coffee MP Room Foyer Registration Building #2 Lobby

9:00am AKST

The Chisel Bootcamp - Presented by Richard Lin MP Room 5 Becoming a Chisel Developer - Presented by Schuyler Eldridge, IBM MP Room 1

10:00am AKST

Coffee Break MP Middle

10:15am AKST

Advanced and New Chisel Features - Presented by Adam Izraelevitz, SiFive MP Room 1 The Chisel Bootcamp continued - Presented by Richard Lin MP Room 5

11:00am AKST

Chipyard and FireSim - Presented by Alon Amid and Sagar Karandikar, UC Berkeley MP Room 1

12:00pm AKST

Lunch MP Middle

1:00pm AKST

HAMMER: A Resusable Methodology for Physical Design - Presented by Colin Schmidt, UC Berkeley) MP Room 1 The Chisel Bootcamp continued - Presented by Richard Lin MP Room 5

2:00pm AKST

Writing a FIRRTL Transform - Presented by Albert Magyar, UC Berkeley MP Room 1

3:00pm AKST

Coffee Break MP Middle

3:15pm AKST

The Chisel Bootcamp continued - Presented by Richard Lin MP Room 5 Demos - Presented by Chick Markley MP Room 1

4:00pm AKST

Event Wrap Up and Summary MP Room 1